1. Field of the Invention
The present invention relates to computer systems and, more particularly, to virtual machine systems which provide for instruction processing in multiple levels of virtual machines. More particularly, the present invention is directed to the efficient use of a translation lookaside buffer (TLB) for address translation.
2. Description of the Prior Art
Mainframe computer systems such as the IBM 3090 computer system comprise a plurality of processors and large random access and sequential access storage devices. These large systems ar capable of processing a large number of tasks in a short period of time. It is frequently desirable to divide this host processing power into separate partitions or "virtual machines" that can be operated by different users. The division is accomplished by the use of host control program softward such as the IBM Virtual Machine/Extended Architecture (VM/XA) system product. Each of the virtual machines defined above can accept a "guest" operating system that may be different from the host operating system. Thus, for example, if the host is running the VM/XA operating system, the guest could operate the IBM MVS/XA system program. The guest virtual machines may in turn be divided into additional virtual machines for performance of certain tasks.
The host control program or operating system is typically referred to as the level 0 machine. A guest operation on the host is typically referred to as a level 1 guest and guests built upon the first guest as level 2 guest systems. The operating systems operating at levels 1 or 2 issue instructions that, they believe, are causing a real access to a processor or memory. The IBM System/370 architecture manages this through a process known as interpretive execution of the virtual machine instructions. The System/370 architecture is described in the IBM Publication GA22-7000. The IBM System/370-XA implementation of interpretive execution is described in IBM Publication SA22-7095.
Interpretive execution requires the translation of instructions and memory addresses from the guest machine to the underlying real machine and real storage. An example of the translations required is the translation of memory addresses from the guest machine to real storage. U.S. Pat. No. 4,456,954, issued on June 26, 1984 and assigned to the assignee of this application, describes interpretive execution and address translation under interpretive execution and is incorporated herein by reference.
The host machine initiates a guest operating system through a Start Interpretive Execution (SIE) instruction. The SIE instruction invokes interpretive execution hardware in the host causing the host to enter interpretive execution mode for the purpose of executing a program in a level 1 guest. SIE provides for the mapping of addresses by the level 1 virtual machine. In a like manner, a level 1 guest can be a host for a level 2 guest.
Each virtual machine to be operated as a guest of the host machine is described in a state description maintained in real storage. When an SIE instruction is encountered, the state description is used to establish the virtual machine environment for execution. At the same time, the existing host environment must be saved so it can be restored upon exit from the virtual machine. Upon completion of the SIE instruction, the current status of the guest virtual machine must be stored in the state description and the previous host environment restored to the real machine.
Among the interpretive execution facilities are dynamic address translation and guest timing services. Dynamic address translation is the process which translates a guest virtual address into a host real address allowing access to the real storage in the machine. The IBM System/370 employs a virtual memory mechanism in which real memory is divided into pages of a constant size, e.g., 4K bytes, which are addressed by segment and page indices. Thus, the virtual address of a memory location will be represented as a segment table index value, a page table index value, and a displacement within the page. To locate the actual data, the segment table, page table, and memory page must each be accessed. If the virtual address is specified in a guest operating system, the address that guest believes to be a real address must be further translated by the lower level guests and the host machine. As a result, several steps of address translation must occur as shown by the arrows in FIG. 3.
Address translation can be made more efficient by the use of a translation lookaside buffer (TLB). The translation lookaside buffer captures the results of dynamic address translation and provides a shortcut for future guest address translations. The TLB has a limited capacity, so only a certain number of recent translations are maintained (e.g. 512). The System/370 hardware provides the ability to test whether or not a translation from virtual to real for the virtual address request is available in the TLB. If the translation is available, it is used and dynamic address translation is bypassed. This can result in significant time savings. The translation lookaside buffer maintains several pieces of information including an indicator of whether the entry is for the host system or a guest, the logical address translated, the real address that resulted from the translation, and the segment table origin (STO) address of the logical address.